ECEn 543 Schedule

Winter 2006

Note: All dates in bold are Mondays

Date

Topic

Reading

Handout/Topic

Homework

1/9

Introduction

1-16

 

 

1/11

CMOS Operation

16-42

 

1.7, 1.8, 1.10

1/13

Device Equations

42-61

 

1.11, 1.12

1/16

Holiday

 

 

 

1/18

CMOS Processing

82-94

 

2.1, 2.2, 2.3

1/20

CMOS Layout

96-105

 

2.4, 2.5, 2.6

1/23

Design Rules

105-115

 

2.10, 2.16

1/25

Substrate Noise

115-121

Spice Examples

Spice 1

1/27

Review

 

 

 

1/30

Current Mirrors

125-134

 

3.1, 3.2, 3.3

2/01

Differential Stage

135-146

 

3.6, 3.7

2/03

Examples

Signal Flow Graphs(handout)

 

Flow Graph 2

2/06

Cascode Stage

146-154

 

3.10, 3.11, 3.12

2/08

Examples

154-163

 

Opamp Design Exercise

2/10

Examples

163-176

 

 

2/13

Review

 

 

 

2/15

Midterm I

 

 

 

2/17

Electronic Noise

181-184

 

4.1, 4.2

2/21(T)

Noise Integration (no class)

184-204

 

4.8

2/22

Noise Examples

204-216

 

4.14, Special Spice/Noise HW

2/24

Classical Op-amp

221-232

 

5.1, 5.2, 5.3

2/27

Compensation

232-236

 

5.10, 5.12

3/01

Pole-Zero Analysis

236-242, Lecture Notes

Lecture Notes

Compensation Exercise

3/03

Examples

242-250, Lecture Notes

Pole Zero

Pole Zero Exercise

3/06

Root Locus

Lecture Notes

Root Locus

Root Locus Exercise

3/08

Examples

Lecture Notes

 

TBA

3/10

Spice Examples

Lecture Notes

 

Spice Exercise

3/13

Output Stages

Lecture Notes

 

TBA

3/15

Review

 

 

 

3/17

 

 

 

Buffer Stage Design (part of Midterm II)

3/20

Midterm II (Quiz)

 

 

 

3/22

 

 

 

 

3/24

 

256-270

 

6.7, 6.8, Special Feedback Problem

3/27

 

 

 

 

3/29

 

 

 

 

3/31

 

 

 

 

4/03

 

 

 

 

4/05

 

 

 

 

4/07

 

 

 

 

4/10

 

 

 

 

4/12

 

 

 

 

4/14

 

 

 

 

4/17

Last Class